1. Field of the Invention
The present invention relates to data transfer apparatuses, and, more particularly, to data transfer apparatuses designed with consideration given to signal delays over data signal lines.
2. Description of the Related Art
Recent increases in computer processing speed require a faster data transfer rate in data transfer apparatuses. Generally, however, the longer the signal line between a data sending unit and a data receiving unit, the greater the signal delay over the signal line. This signal delay represents overhead that cannot be ignored in a data transfer operation over the signal line. Thus, a data transfer circuit incorporating the signal line must be designed with the delay time taken into account.
Referring to FIG. 6, a block diagram is shown that illustrates a prior art problem of conventional data transfer apparatuses. A data sending unit 61 transfers data to data receiving units 62 and 63, which may be memory modules for example, via a bus signal line 64. The data from the data sending unit 61 are sent from a flip-flop circuit 65 on a clock Ta. Upon receipt of a clock Tb, a flip-flop circuit 66 of the data receiving unit 62 and a flip-flop circuit 67 of the data receiving unit 63 capture the data.
FIG. 7 shows a timing chart illustrating operational timings of the above-mentioned prior art technology. As shown in the figure, there is a delay time Td between the moment when the data are received by the flip-flop circuit 66 and the moment when the data are received by the flip-flop circuit 67. The delay is caused by a difference in the lengths of the wirings running from the data sending unit 61 to the data receiving unit 62, and from the data sending unit 61 to the data receiving unit 63.
Consequently, a clock Tb, which is generated with consideration given to the setup time of an input to the flip-flop circuit 67 from arrival to capture of data, is applied to data inputs of the data receiving units 62 and 63 containing the flip-flop circuits 66 and 67, respectively, to capture the data. Thus, the data transfer apparatus of FIG. 6 is designed by taking into account the difference Td between delay times for the capture clock pulses of the receiving side.
However, since this conventional technique performs synchronized data transfer, the speed of the data transfer interval is constrained by the delay caused by the spatial difference between mounting positions of the sending and receiving units. That is, the data transfer can be completed no faster than the time necessary to transfer between the most distant sending and receiving units.